Non Contiguous MCQ Quiz in বাংলা - Objective Question with Answer for Non Contiguous - বিনামূল্যে ডাউনলোড করুন [PDF]
Last updated on Mar 17, 2025
Latest Non Contiguous MCQ Objective Questions
Top Non Contiguous MCQ Objective Questions
Non Contiguous Question 1:
A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4-way set associative. The minimum size of the TLB tag is
Answer (Detailed Solution Below)
Non Contiguous Question 1 Detailed Solution
Data:
Virtual address space = 32 bits
Page size = 4 KB = 212 B
number of entries in TLB = number of lines = 128
set associative = 4 -way
Formula:
number of bits = ⌈log2 n⌉
Number of sets in cache = \(\frac{number\; of\; lines}{set\; associativity}\)
Virtual address = tag + set + page offset (in bits)
Calculation:
set = \(\frac{128}{4} = 2^{5}\)
number of bits in set = 5
32 = tag + 5 + 12
∴ tag = 15 bits
The minimum size of the TLB tag is 15 bits.
Non Contiguous Question 2:
The minimum number of page frames that must be allocated to a running process in a virtual memory environment is determined by
Answer (Detailed Solution Below)
Non Contiguous Question 2 Detailed Solution
Instruction set architecture:
- The Absolute minimum number of frames that a process must be allocated is completely dependent on System architecture.
- The Number of pages that could be touched by a single instruction.
- For no indirect addressing, at least two pages in physical memory, that is, one for instruction (code part) and another for if the data references memory.
- If there is one level of indirection, then it will need at least three pages one for the instruction(code) and another two for the indirect addressing and so on.
- Therefore, the instruction set architecture determines the minimum number of page frames that must be allocated to a running process in a virtual memory environment.
Non Contiguous Question 3:
If a processor has 32-bit virtual address, 28-bit physical address, 2 kB page size. How many bits are required for the virtual, physical page number?
Answer (Detailed Solution Below)
Non Contiguous Question 3 Detailed Solution
Data:
Virtual address space (VAS) = 232 Byte
Physical address space (PAS) = 228 Byte
Page size (PS) = 211 Byte
Formula:
\({\rm{number\;of\;pages\;}} = {\rm{P}} = \frac{{{\rm{VAS}}}}{{{\rm{PS}}}}\)
\({\rm{number\;of\;frames}} = {\rm{F}} = \frac{{{\rm{PAS}}}}{{{\rm{PS}}}}\)
Bits required for the virtual page number = ⌈ log2 P ⌉
Bits required for the physical page number = ⌈ log2 F⌉
Calculation:
\({\rm{P}} = \frac{{{2^{32}}}}{{{2^{11}}}} = {2^{21}}\)
Bits required for the virtual page number = ⌈ log2 221 ⌉ = 21
\({\rm{F}} = \frac{{{2^{28}}}}{{{2^{11}}}} = \;{2^{17}}\)
Bits required for the physical page number = ⌈ log2 217 ⌉ = 17Non Contiguous Question 4:
Which of the following is CORRECT ?
Answer (Detailed Solution Below)
Non Contiguous Question 4 Detailed Solution
The correct answer is option 4.
This phenomenon is called Belady's Anomaly.
Belady Anomaly- In FIFO(First in First out) page replacement algorithm, if we sometimes increase the page frame then page fault also increases.
Refer to the diagram below for its explanation-
Request Elements:- 1,2,3,4,1,2,5,1,2,3,4,5.
Using 3 frames.
F = Page Fault, H = Page Hit
Total page faults = 9
But with 4 frames:
Total pages faults become 10.
Remember, This only happens with the FIFO algorithm, and that too sometimes, not always.
Why option 1 is wrong-
Page fault rate always decreases with an increase in the number of frames, but option 1 contradicts this statement.
Why option 2 is wrong-
Page fault is always dependent on the number of frames,
Why option 3 is wrong-
Page fault rates have no direct relationship with the degree of multiprogramming.
Non Contiguous Question 5:
Consider a single-level page table system. with the page table stored in the memory. If the hit rate to TLB is 80%, and it takes 15 nanoseconds to search the TLB. and 150 nanoseconds to access the main memory, then what is the effective memory access time, in nanoseconds ?
Answer (Detailed Solution Below)
Non Contiguous Question 5 Detailed Solution
Data:
TLB hit ratio = p = 0.8
TLB access time = 15 nanoseconds
Memory access time = m = 150 milliseconds
Formula:
EMAT = p × (t + m) + (1 – p) × (t + m + m)
Calculation:
EMAT = 0.8 × (15 + 150) + (1 – 0.8) × (15 + 150 + 150)
EMAT = 195 nanoseconds.
Important points:
During TLB hit
Frame number is fetched from the TLB (15 ms)
and page is fetched from physical memory (150 ms)
During TLB miss
TLB no entry matches (15 ms)
Frame number is fetched from the physical memory (150 ms)
and pages are fetched from physical memory (150 ms)Non Contiguous Question 6:
A phenomenon in which a process spends more time on swapping pages rather than on executing is called:
Answer (Detailed Solution Below)
Non Contiguous Question 6 Detailed Solution
Concept:
Thrashing occurs when a computer's virtual memory resources are overused, leading to a constant state of paging and page faults, inhibiting most application-level processing. This causes the performance of the computer to degrade or collapse. The situation can continue indefinitely until either the user closes some running applications or the active processes free up additional virtual memory resources.
When the working set is a small percentage of the system's total number of pages, virtual memory systems work most efficiently and an insignificant amount of computing is spent resolving page faults. As the working set grows, resolving page faults remains manageable until the growth reaches a critical point. Then faults go up dramatically and the time spent resolving them overwhelms time spent on the computing the program was written to do. This condition is referred to as thrashing.
Hence Option 4 is correct
Additional Information
Segmentation is a memory management technique in which, the memory is divided into the variable size parts. Each part is known as segment which can be allocated to a process. The details about each segment are stored in a table called as segment table.
As processes are loaded and removed from memory, the free memory space is broken into little pieces. It happens after sometimes that processes cannot be allocated to memory blocks considering their small size and memory blocks remains unused. This problem is known as Fragmentation.
Paging is a storage mechanism that allows OS to retrieve processes from the secondary storage into the main memory in the form of pages. In the Paging method, the main memory is divided into small fixed-size blocks of physical memory, which is called frames.
Non Contiguous Question 7:
Consider a process of 200 KB which has 2 segments each segment size is 256 KB. Which of the following is the correct number of bytes of overhead in segmented paging if the page table entry is 4B, the segment table entry is 2B and Page size is 2KB.
Answer (Detailed Solution Below)
Non Contiguous Question 7 Detailed Solution
Data:
Page Size = 2 KB
segment size = 256 KB
number of segment = 2
Page table entry(PTE) = 2 KB
Segment Entry size = 2 B:
Calculation:
Number of Pages in a segement = \(\frac{{256KB}}{{2KB}} = 128 = {2^7}\)
Each Table will have its own page table.
Number of entries in a page table = Number of pages in a segment 
= Page Table Size = (Number of Entries * PTE Size) = \({2^7} × {2^2} = {2^9} = 512B\)
Size of segment table = Number of entries in segment table × size of each entry =
∴ Size of segment table = \(2 × 2 = 4B\)
Total Overhead of a page table = 512 + 4 = 516 B
Non Contiguous Question 8:
Consider a system where the page fault service time is 200ms, and the main memory access time is 10ms. The translation look aside buffer is added to improve the performance. The 80% references are found in the TLB and that of the remaining 10% cause page faults. The TLB access time is 2ms and the page table access time is negligible. Then what is the effective memory access time (EMAT)?
Answer (Detailed Solution Below)
Non Contiguous Question 8 Detailed Solution
The question can be visualize by using diagram as shown below -
Data:
TLB hit ratio = 80% , TLB miss ratio = 20%
TLB access time = 2ms
Main memory access time = 10ms
Page fault rate = 10% , Page miss rate = 90%
Page fault service time = 200ms
Calculation :
EMAT = TLB hit ratio (TLB time + main memory time) + TLB miss ratio [ TLB time + page fault rate(page fault service time) + page miss rate (main memory time) ]
EMAT = 0.8(2 + 10) + 0.2[ 2 + 0.1(200) + 0.9(10) ]
EMAT = 9.6 + 6.2
EMAT = 15.8 ms
Non Contiguous Question 9:
Consider a computer system with 32-bit virtual addressing and a page size of sixty-four kilobytes. The computer system has a one-level page table per process with each page table entry of 6 bytes. If the maximum physical memory size supported by this paging system is given to be 128 petabytes (257 bytes), how many bits can be used for flags and permissions within a page table entry?
Answer (Detailed Solution Below)
Non Contiguous Question 9 Detailed Solution
Data:
Virtual address space or process size= 232 Bytes
Page size = 64KB =216 Bytes
Main memory size = 257 bytes
Page table entry size = 6 Bytes = 48 bits
Concept:
|
Flag and permission bits |
Frame number |
|
Page table entry |
|
Explanation:
- Total number of frame = \(\frac{{{2^{57}}}}{{{2^{16}}}} = {2^{41}}\) so 41 bits are needed to address particular frame number in main memory.
- Page table entry size = 48 bits so if we subtract frame number bits then we can get flag and permission bits.
- Flag and permission bits = 48bits - 41bits = 7bits
Option 3 is the correct answer.
Non Contiguous Question 10:
Consider a paging system where translation look aside buffer (TLB) a special type of associative memory is used with hit ratio of 80%.
Assume that memory reference takes 80 nanoseconds and reference time to TLB is 20 nanoseconds. What will be the effective memory access time given 80% hit ratio?Answer (Detailed Solution Below)
Non Contiguous Question 10 Detailed Solution
Data:
TLB hit ratio = 0.8
TLB miss ration = 0.2
TLB reference time = 20 ns
Main Memory reference time = 80 ns
Formula:
Effective memory access time (EMAT)
= TLB hit (TLB time + Main memory time) + TLB miss (TLB time + 2 × Main memory time)
Calculation:
EMAT = 0.8 (20 + 80) + 0.2 (20 + 80 + 80)
= 80 + 36
∴ EMAT= 116 ns